1. Field of the Invention
The present invention relates to a manufacturing method of a semiconductor device and, more particularly to a manufacturing method of a semiconductor device in which a wiring layer composed of a metal film is formed on an interlayer insulating film.
2. Description of the Related Art
Large scale integrated circuits (LSIs) known as the representative of the semiconductor devices can roughly be classified into memory products and logic products. Together with the progress of manufacturing technologies of semiconductor devices in recent years, the development, especially in the former, is remarkable. The semiconductor memories are classified into dynamic random access memories (DRAMS) and static random access memories (SRAMS). Since it is possible in the DRAM to take more extensive advantage of high degree of integration than in the SRAM and hence realize more cost reduction than in the SRAM, it is being applied widely to various kinds of memory devices in information equipment or the like.
In a DRAM, one memory cell is constituted by a memory cell transistor composed of a metal oxide semiconductor (MOS) transistor performing switching operation, and a capacitor connected to one diffusion region of the memory cell transistor, and information is stored by the memory cell as electrical charges into the capacitor. Here, in the DRAM, information to be written is transformed to the capacitor via the memory cell transistor from a bit line connected to the other diffusion region of the memory cell transistor, and information stored in the capacitor is read out there from via the transistor to the bit line. The bit line which serves as the path for writing and reading information is thus required to be in resistance as small as possible, for the purpose of increasing the operation speed. In recent years, therefore, a tungsten (W) film which has been used preferentially. The W film is formed as a bit line as a bit line on an interlayer insulating film and connected to the cell transistor through a contact hole provided in the interlayer insulating film.
It has been, however, observed that the W film often peels off from the interlayer insulating film occurs.
In order to remove such drawback, the Japanese Laid Open, (Kokai) Patent Publication Hei 9-289247 proposed an improved method of producing a DRAM. The description will be now made on such method with reference to FIGS. 10A to 10D.
As shown in FIG. 10A, after formation of wiring layers 52 each consisting of a polycide and an aluminum alloy containing a slight amount of metal such as copper on an insulating film 51, a silicon oxide film 53 as an interlayer insulating film is formed on the wirings 52 by a high density plasma chemical vapor deposition (HDP-CVD) method. Next, as shown in FIG. 10B, the silicon oxide film 53 is flattened by chemical mechanical polishing method.
Next, as shown in FIG. 10C, contact holes 54 are formed in the silicon oxide film 53 by photolithography.
In the conventional method, wiring material was deposited just after the formation of the contact holes. However, when a W film as the wiring material was deposited, the W film peeled off from the interlayer insulating film during the deposition of the W film. This is because gases such as hydrogen and argon confined in the silicon oxide film 53 as the interlayer insulating film were degassed and pushed up the W film during the deposition of the W film at a temperature of about 400xc2x0 C.
Therefore, just after the formation of the contact holes 54 in FIG. 10C, gases such as hydrogen and argon held in the silicon oxide film 53 are degassed by subjecting the wafer to an annealing in a nitrogen atmosphere at a temperature in the range of 350 to 450xc2x0 C. (degrees Centigrade) for 60 min.
Next, as shown in FIG. 10D, after forming an adhesion layer 55 consisting of Ti/TiN by sputtering or the like, a W film 56 is formed by a chemical vapor deposition (CVD).
According to this method, by subjecting the wafer to an annealing at a temperature in the range of 350 to 450xc2x0 C. prior to the formation of the W film, it is possible to remove (degas) gases such as hydrogen and argon confined in the silicon oxide film 53 during formation of the silicon oxide film 53 by the HDP-CVD, so that there take place no such degassing at formation of the W film 56. Accordingly, this prior art claims that there will not occur peeling of the W film 56 due to push of gases at the degassing.
Although it is not described in the above prior art, the W film needs to be patterned to wirings after the process of FIG. 10D. When a metal film such as aluminum is used as wirings, the metal film can be patterned employing a resist film as a mask. However it is not appropriate that a resist film is employed as a mask for patterning the W film because it is not possible to obtain a sufficient selectivity between the resist film and the W film. Therefore, a silicon nitride film is used as a mask for patterning the W film.
It was found by the present inventor that when the silicon nitride film as the mask for patterning the W film is formed after formation of the W film according to the method in the above prior art, the W film actually peels off from the interlayer insulating film. Since it is difficult that the silicon nitride film is formed in low temperature when a thermal reaction is employed, the silicon nitride film is usually formed in temperature range of 700 to 750xc2x0 C. When the wafer is subjected to a heat treatment at such high temperature after formation of the W film, gases including oxygen which have been confined in the interlayer insulating film are degassed to the outside, and the adhesion of the W film to the interlayer insulating film is aggravated due to oxidation of the W film by the gases including oxygen. Moreover, it was found that gases including oxygen held in the interlayer insulating film is scarcely desorbed at a temperature in the range of 350 to 450xc2x0 C., and these gases are desorbed in a large quantity at higher temperatures than in the quoted range. In the above prior art, the heat treatment in the quoted temperature range is performed for the sole purpose of preventing peeling due to push-up of the W film caused by degassing of hydrogen or argon, and it utterly lacks the recognition as to the peeling problem caused by the degassing of gases including oxygen from the interlayer insulating film. As a result, according to the manufacturing method disclosed in the above prior art, gases including oxygen are held in large quantity in the layer insulting film even after an annealing at a temperature in the range of 350 to 450xc2x0 C., and if the wafer is subjected to a heat treatment at a higher temperature, the W film will be oxidized by the degassing of gases including oxygen and will be peeling off from the interlayer insulating film.
The object of the present invention which was motivated by the above circumstance is to provide a manufacturing method of a semiconductor device capable of preventing the peeling of the W film caused by the gases including oxygen held in the interlayer insulating film even if the wafer is subjected to a heat treatment at higher temperatures after formation of the W film.
The method according to the present invention includes forming an insulating film over a semiconductor substrate, oxygen being introduced into the insulating film during formation of the insulating film, removing the oxygen from the insulating film to provide an oxygen-removed insulating film, and forming a metal film on the oxygen-removed insulating.
The removing the oxygen is performed by an annealing treatment.
The annealing treatment is performed at a temperature which is not lower than a heat treatment which may be carried out in a later step than formation of said metal film.
The later step includes forming a silicon nitride film over the metal film.
The insulating film is formed of a CVD silicon oxide film.
Moreover, the method according to the invention includes forming a first insulating film over a semiconductor substrate, forming a metal film on the first insulating film, and forming a second insulating film on the metal film at a first temperature, wherein annealing treatment is performed on the first insulating film before the metal film is formed, the annealing treatment being carried out at a second temperature which is not lower than the first temperature.
The second insulating is used as a mask for selectively etching the metal film to form a wiring layer.
The method further comprises selectively etching the second insulating film to form a mask pattern and selectively etching the method film by use of the mask pattern to form a wiring layer, the first insulating film being a CVD silicon oxide film and the second insulating film being a silicon nitride film.
The second insulating film is formed at a temperature in the range of 700 to 750xc2x0 C., and the annealing treatment is carried out at a temperature in the range of 700 to 800xc2x0 C.
The metal film can comprise at least one of a W film, a WN film, a TiN film and a Ti film.
According to such methods, gases including oxygen held in the insulating film under the metal film are removed in advance prior to the formation of the metal film, so that even if wafer is subjected to a high temperature treatment such as the formation of the silicon nitride film after formation of the metal film, there will occur no degassing of oxygen form the insulating film. As a result, it is possible to prevent peeling of the metal film from the insulating film due to oxidation of the metal film by the oxygen.